/**
  ******************************************************************************
  * @file    ys32f030_rcc.h
  * @author  YSPRING Application Team
  * @version V1.0.1
  * @date    2023.6.25
  * @brief   This file contains all the functions prototypes for the RCC 
  *          firmware library.
  ******************************************************************************
  */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __YS32F030_RCC_H
#define __YS32F030_RCC_H

#ifdef __cplusplus
 extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "ys32f030.h"

#if !defined  (HSE_VALUE)     
#define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/
#endif /* HSE_VALUE */

/**
 * @brief In the following line adjust the External High Speed oscillator (HSE) Startup 
   Timeout value 
   */
#if !defined  (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT   ((uint16_t)0x5000) /*!< Time out for HSE start up */
#endif /* HSE_STARTUP_TIMEOUT */

/**
 * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup 
   Timeout value 
   */
#if !defined  (HSI_STARTUP_TIMEOUT)
#define HSI_STARTUP_TIMEOUT   ((uint16_t)0x5000) /*!< Time out for HSI start up */
#endif /* HSI_STARTUP_TIMEOUT */

#define HSI16_VALUE  ((uint32_t)16000000)
#define HSI24_VALUE  ((uint32_t)24000000)
#define HSI36_VALUE  ((uint32_t)36000000)
#define HSI48_VALUE  ((uint32_t)48000000)

#if !defined  (HSI_VALUE) 
#define HSI_VALUE  ((uint32_t)16000000) /*!< Value of the Internal High Speed oscillator in Hz.
                                             The real value may vary depending on the variations
                                             in voltage and temperature.  */
#endif /* HSI_VALUE */

#if !defined  (LSI_VALUE) 
#define LSI_VALUE  ((uint32_t)32768)    /*!< Value of the Internal Low Speed oscillator in Hz
                                             The real value may vary depending on the variations
                                             in voltage and temperature.  */
#endif /* LSI_VALUE */

#if !defined  (LSE_VALUE) 
#define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */

/** @addtogroup YS32F030_StdPeriph_Driver
  * @{
  */

/** @addtogroup RCC
  * @{
  */

/* Exported types ------------------------------------------------------------*/

typedef struct
{
  uint32_t SYSCLK_Frequency;
  uint32_t HCLK_Frequency;
  uint32_t PCLK_Frequency;
}RCC_ClocksTypeDef;

/* Exported constants --------------------------------------------------------*/

/** @defgroup RCC_Exported_Constants
  * @{
  */

/** @defgroup RCC_HSE_configuration 
  * @{
  */
#define RCC_HSE_OFF                      ((uint32_t)0x00000000)
#define RCC_HSE_ON                       ((uint32_t)RCC_CR_HSEON)
#define RCC_HSE_Bypass                   ((uint32_t)RCC_CR_HSEBYP)
#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
                         ((HSE) == RCC_HSE_Bypass))

/**
  * @}
  */ 
 
/** @defgroup RCC_PLL_Clock_Source 
  * @{
  */
#define RCC_PLLSource_HSE                RCC_PLLCFGR_PLLSRC
#define RCC_PLLSource_HSI                ((uint32_t)0x00000000)

#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI)      || \
                                   ((SOURCE) == RCC_PLLSource_HSE))
/**
  * @}
  */ 

/** @defgroup RCC_PLL_Multiplication_Factor 
  * @{
  */
#define RCC_PLLMul_2                    ((uint32_t)0x00)
#define RCC_PLLMul_4                    RCC_CFGR_PLLMUL
#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_4))
/**
  * @}
  */

/** @defgroup RCC_System_Clock_Source 
  * @{
  */
#define RCC_SYSCLKSource_HSI             (RCC_CFGR_SW_HSISYS)
#define RCC_SYSCLKSource_HSE             (RCC_CFGR_SW_HSE)
#define RCC_SYSCLKSource_PLL             (RCC_CFGR_SW_PLLCLK)
#define RCC_SYSCLKSource_LSI             (RCC_CFGR_SW_LSI)
#define RCC_SYSCLKSource_LSE             (RCC_CFGR_SW_LSE)

#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI)   || \
                                      ((SOURCE) == RCC_SYSCLKSource_HSE)   || \
                                      ((SOURCE) == RCC_SYSCLKSource_PLL)   || \
                                      ((SOURCE) == RCC_SYSCLKSource_LSI)   || \
                                      ((SOURCE) == RCC_SYSCLKSource_LSE))
/**
  * @}
  */

/** @defgroup RCC_AHB_Clock_Source
  * @{
  */
#define RCC_SYSCLK_Div1                  (RCC_CFGR_HPRE_1)
#define RCC_SYSCLK_Div2                  (RCC_CFGR_HPRE_2)
#define RCC_SYSCLK_Div4                  (RCC_CFGR_HPRE_4)
#define RCC_SYSCLK_Div8                  (RCC_CFGR_HPRE_8)
#define RCC_SYSCLK_Div16                 (RCC_CFGR_HPRE_16)
#define RCC_SYSCLK_Div64                 (RCC_CFGR_HPRE_64)
#define RCC_SYSCLK_Div128                (RCC_CFGR_HPRE_128)
#define RCC_SYSCLK_Div256                (RCC_CFGR_HPRE_256)
#define RCC_SYSCLK_Div512                (RCC_CFGR_HPRE_512)
#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1)  || ((HCLK) == RCC_SYSCLK_Div2)   || \
                           ((HCLK) == RCC_SYSCLK_Div4)  || ((HCLK) == RCC_SYSCLK_Div8)   || \
                           ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64)  || \
                           ((HCLK) == RCC_SYSCLK_Div128)|| ((HCLK) == RCC_SYSCLK_Div256) || \
                           ((HCLK) == RCC_SYSCLK_Div512))
/**
  * @}
  */ 

/** @defgroup RCC_APB_Clock_Source
  * @{
  */
#define RCC_HCLK_Div1                    (RCC_CFGR_PPRE_1)
#define RCC_HCLK_Div2                    (RCC_CFGR_PPRE_2)
#define RCC_HCLK_Div4                    (RCC_CFGR_PPRE_4)
#define RCC_HCLK_Div8                    (RCC_CFGR_PPRE_8)
#define RCC_HCLK_Div16                   (RCC_CFGR_PPRE_16)
#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
                           ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
                           ((PCLK) == RCC_HCLK_Div16))
/**
  * @}
  */
         
/** @defgroup RCC_Interrupt_IT
  * @{
  */
#define RCC_IT_LSERDY                    RCC_CIER_LSERDYIE
#define RCC_IT_HSIRDY                    RCC_CIER_HSIRDYIE 
#define RCC_IT_HSERDY                    RCC_CIER_HSERDYIE
#define RCC_IT_PLLRDY                    RCC_CIER_PLLRDYIE 

#define RCC_IT_HSECSSF                   RCC_CIFR_CSSF
#define RCC_IT_LSECSSF                   RCC_CIFR_LSECSSF

#define IS_RCC_IT(IT) (((IT) == RCC_IT_LSERDY) || ((IT) == RCC_IT_HSIRDY) || \
                       ((IT) == RCC_IT_HSERDY) || ((IT) == RCC_IT_PLLRDY))
                            
#define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00)

#define IS_RCC_IT2(IF) (((IF) == RCC_IT_LSERDY) || ((IF) == RCC_IT_HSIRDY) || \
                        ((IF) == RCC_IT_HSERDY) || ((IF) == RCC_IT_PLLRDY) || \
                        ((IF) == RCC_IT_HSECSSF)||((IF) == RCC_IT_LSECSSF))
/**
  * @}
  */
  
/** @defgroup RCC_LSE_Configuration 
  * @{
  */
#define RCC_LSE_OFF                      ((uint32_t)0x00000000)
#define RCC_LSE_ON                       RCC_BDCR_LSEON
#define RCC_LSE_Bypass                   ((uint32_t)(RCC_BDCR_LSEON | RCC_BDCR_LSEBYP))
#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
                         ((LSE) == RCC_LSE_Bypass))
/**
  * @}
  */

/** @defgroup RCC_RTC_Clock_Source
  * @{
  */
#define RCC_RTCCLKSource_NoClock         (RCC_BDCR_RTCSEL_Noclock)
#define RCC_RTCCLKSource_LSE             (RCC_BDCR_RTCSEL_LSE)
#define RCC_RTCCLKSource_LSI             (RCC_BDCR_RTCSEL_LSI)
#define RCC_RTCCLKSource_HSE_Div128      (RCC_BDCR_RTCSEL_HSEdividedby128)

#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_NoClock) || \
                                      ((SOURCE) == RCC_RTCCLKSource_LSE)     || \
                                      ((SOURCE) == RCC_RTCCLKSource_LSI)     || \
                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div128))
/**
  * @}
  */

/** @defgroup RCC_IO_Peripherals 
  * @{
  */
#define RCC_AHB2Periph_GPIOA               RCC_IOPENR_GPIOAEN
#define RCC_AHB2Periph_GPIOB               RCC_IOPENR_GPIOBEN
#define RCC_AHB2Periph_GPIOC               RCC_IOPENR_GPIOCEN
#define RCC_AHB2Periph_GPIOF               RCC_IOPENR_GPIOFEN

#define IS_RCC_IO_PERIPH(PERIPH) (((PERIPH) == RCC_AHB2Periph_GPIOA)  || \
                                  ((PERIPH) == RCC_AHB2Periph_GPIOB)  || \
                                  ((PERIPH) == RCC_AHB2Periph_GPIOC)  || \
                                  ((PERIPH) == RCC_AHB2Periph_GPIOF))
  
/** @defgroup RCC_AHB_Peripherals 
  * @{
  */
#define RCC_AHBPeriph_CRC                RCC_AHBENR_CRCEN
#define RCC_AHBPeriph_DMA                RCC_AHBENR_DMAEN
#define IS_RCC_AHB_PERIPH(PERIPH) (((PERIPH) == RCC_AHBPeriph_CRC) || \
                                   ((PERIPH) == RCC_AHBPeriph_DMA))
                                      
/**
  * @}
  */

/** @defgroup RCC_APB2_Peripherals 
  * @{
  */
#define RCC_APB2Periph_COMP4             RCC_APBENR2_COMP4EN 
#define RCC_APB2Periph_COMP3             RCC_APBENR2_COMP3EN 
#define RCC_APB2Periph_LED               RCC_APBENR2_LEDEN   
#define RCC_APB2Periph_COMP2             RCC_APBENR2_COMP2EN 
#define RCC_APB2Periph_COMP1             RCC_APBENR2_COMP1EN 
#define RCC_APB2Periph_ADC               RCC_APBENR2_ADCEN   
#define RCC_APB2Periph_TIM17             RCC_APBENR2_TIM17EN 
#define RCC_APB2Periph_TIM16             RCC_APBENR2_TIM16EN 
#define RCC_APB2Periph_TIM15             RCC_APBENR2_TIM15EN 
#define RCC_APB2Periph_TIM14             RCC_APBENR2_TIM14EN 
#define RCC_APB2Periph_UART1             RCC_APBENR2_UART1EN 
#define RCC_APB2Periph_SPI1              RCC_APBENR2_SPI1EN  
#define RCC_APB2Periph_TIM1              RCC_APBENR2_TIM1EN  
#define RCC_APB2Periph_SYSCFG            RCC_APBENR2_SYSCFGEN

#define IS_RCC_APB2_PERIPH(PERIPH) (((PERIPH) == RCC_APB2Periph_COMP4) || ((PERIPH) == RCC_APB2Periph_COMP3)   || \
                                    ((PERIPH) == RCC_APB2Periph_LED)   || ((PERIPH) == RCC_APB2Periph_COMP2)   || \
                                    ((PERIPH) == RCC_APB2Periph_COMP1) || ((PERIPH) == RCC_APB2Periph_ADC)     || \
                                    ((PERIPH) == RCC_APB2Periph_TIM17) || ((PERIPH) == RCC_APB2Periph_TIM16)   || \
                                    ((PERIPH) == RCC_APB2Periph_TIM15) || ((PERIPH) == RCC_APB2Periph_TIM14)   || \
                                    ((PERIPH) == RCC_APB2Periph_UART1) || ((PERIPH) == RCC_APB2Periph_SPI1)    || \
                                    ((PERIPH) == RCC_APB2Periph_TIM1)  || ((PERIPH) == RCC_APB2Periph_SYSCFG))

/**
  * @}
  */ 

/** @defgroup RCC_APB1_Peripherals 
  * @{
  */
#define RCC_APB1Periph_LPTIM             RCC_APBENR1_LPTIMEN 
#define RCC_APB1Periph_PWR               RCC_APBENR1_PWREN   
#define RCC_APB1Periph_DBG               RCC_APBENR1_DBGEN   
#define RCC_APB1Periph_I2C2              RCC_APBENR1_I2C2EN  
#define RCC_APB1Periph_I2C1              RCC_APBENR1_I2C1EN  
#define RCC_APB1Periph_UART2             RCC_APBENR1_UART2EN 
#define RCC_APB1Periph_SPI2              RCC_APBENR1_SPI2EN  
#define RCC_APB1Periph_IWDG              RCC_APBENR1_IWDGEN  
#define RCC_APB1Periph_WWDG              RCC_APBENR1_WWDGEN  
#define RCC_APB1Periph_RTC               RCC_APBENR1_RTCAPBEN
#define RCC_APB1Periph_TIM6              RCC_APBENR1_TIM6EN  
#define RCC_APB1Periph_TIM3              RCC_APBENR1_TIM3EN  

#define IS_RCC_APB1_PERIPH(PERIPH) (((PERIPH) == RCC_APB1Periph_LPTIM)|| ((PERIPH) == RCC_APB1Periph_PWR)    || \
                                    ((PERIPH) == RCC_APB1Periph_DBG)  || ((PERIPH) == RCC_APB1Periph_I2C2)   || \
                                    ((PERIPH) == RCC_APB1Periph_I2C1) || ((PERIPH) == RCC_APB1Periph_UART2)  || \
                                    ((PERIPH) == RCC_APB1Periph_SPI2) || ((PERIPH) == RCC_APB1Periph_IWDG)   || \
                                    ((PERIPH) == RCC_APB1Periph_WWDG) || ((PERIPH) == RCC_APB1Periph_RTC)    || \
                                    ((PERIPH) == RCC_APB1Periph_TIM6) || ((PERIPH) == RCC_APB1Periph_TIM3))
                                      
/**
  * @}
  */

/** @defgroup RCC_MCO_Clock_Source
  * @{
  */
#define RCC_MCOSource_NoClock            (RCC_CFGR_MCOSEL_Noclock)
#define RCC_MCOSource_SYSCLK             (RCC_CFGR_MCOSEL_SYSCLK)
#define RCC_MCOSource_HSI                (RCC_CFGR_MCOSEL_HSI)
#define RCC_MCOSource_HSE                (RCC_CFGR_MCOSEL_HSE)
#define RCC_MCOSource_PLLCLK             (RCC_CFGR_MCOSEL_PLLCLK)
#define RCC_MCOSource_LSI                (RCC_CFGR_MCOSEL_LSI)
#define RCC_MCOSource_LSE                (RCC_CFGR_MCOSEL_LSE)

#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_SYSCLK) || \
                                   ((SOURCE) == RCC_MCOSource_HSE)     || ((SOURCE) == RCC_MCOSource_PLLCLK) || \
                                   ((SOURCE) == RCC_MCOSource_LSI)     || ((SOURCE) == RCC_MCOSource_LSE)    || \
                                   ((SOURCE) == RCC_MCOSource_HSI))
/**
  * @}
  */ 

/** @defgroup RCC_MCOPrescaler
  * @{
  */
#define RCC_MCOPrescaler_1            (RCC_CFGR_MCOPRE_1)
#define RCC_MCOPrescaler_2            (RCC_CFGR_MCOPRE_2)
#define RCC_MCOPrescaler_4            (RCC_CFGR_MCOPRE_4)
#define RCC_MCOPrescaler_8            (RCC_CFGR_MCOPRE_8)
#define RCC_MCOPrescaler_16           (RCC_CFGR_MCOPRE_16)
#define RCC_MCOPrescaler_32           (RCC_CFGR_MCOPRE_32)
#define RCC_MCOPrescaler_64           (RCC_CFGR_MCOPRE_64)
#define RCC_MCOPrescaler_128          (RCC_CFGR_MCOPRE_128)

#define IS_RCC_MCO_PRESCALER(PRESCALER) (((PRESCALER) == RCC_MCOPrescaler_1)  || \
                                         ((PRESCALER) == RCC_MCOPrescaler_2)  || \
                                         ((PRESCALER) == RCC_MCOPrescaler_4)  || \
                                         ((PRESCALER) == RCC_MCOPrescaler_8)  || \
                                         ((PRESCALER) == RCC_MCOPrescaler_16) || \
                                         ((PRESCALER) == RCC_MCOPrescaler_32) || \
                                         ((PRESCALER) == RCC_MCOPrescaler_64) || \
                                         ((PRESCALER) == RCC_MCOPrescaler_128))
                                     
/**
  * @}
  */ 

/** @defgroup RCC_Flag 
  * @{
  */
  
//0
#define RCC_FLAG_HSIRDY                  (RCC_CR_HSIRDY)
#define RCC_FLAG_HSERDY                  (RCC_CR_HSERDY)
#define RCC_FLAG_PLLRDY                  (RCC_CR_PLLRDY)

//1
#define RCC_FLAG_LSERDY                  ((RCC_BDCR_LSERDY) | (1<<20))  //bit20~23 is CMD

//2
#define RCC_FLAG_OBLRST                  ((RCC_CSR_OBLRSTF) | (2<<20))
#define RCC_FLAG_PINRST                  ((RCC_CSR_PINRSTF) | (2<<20))
#define RCC_FLAG_PWRRST                  ((RCC_CSR_PWRRSTF) | (2<<20))
#define RCC_FLAG_SFTRST                  ((RCC_CSR_SFTRSTF) | (2<<20))
#define RCC_FLAG_IWDGRST                 ((RCC_CSR_IWDGRSTF)| (2<<20))
#define RCC_FLAG_WWDGRST                 ((RCC_CSR_WWDGRSTF)| (2<<20))

#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_OBLRST )  || \
                           ((FLAG) == RCC_FLAG_PINRST )  || \
                           ((FLAG) == RCC_FLAG_PWRRST )  || \
                           ((FLAG) == RCC_FLAG_SFTRST )  || \
                           ((FLAG) == RCC_FLAG_IWDGRST)  || \
                           ((FLAG) == RCC_FLAG_WWDGRST)  || \
                           ((FLAG) == RCC_FLAG_HSIRDY )  || \
                           ((FLAG) == RCC_FLAG_HSERDY)   || \
                           ((FLAG) == RCC_FLAG_PLLRDY)   || \
                           ((FLAG) == RCC_FLAG_LSERDY))

#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7FF)

/**
  * @}
  */
  
/** @defgroup RCC_Source_Sysclk
  * @{
  */

#define RCC_SOURCE_HSI                  (RCC_CFGR_SW_HSISYS)
#define RCC_SOURCE_HSE                  (RCC_CFGR_SW_HSE)
#define RCC_SOURCE_PLL                  (RCC_CFGR_SW_PLLCLK)
#define RCC_SOURCE_LSI                  (RCC_CFGR_SW_LSI)
#define RCC_SOURCE_LSE                  (RCC_CFGR_SW_LSE)

#define IS_RCC_SOURCE_CLK(CLK) (((CLK) == RCC_SOURCE_HSI)  || ((CLK) == RCC_SOURCE_HSE)  || \
                                ((CLK) == RCC_SOURCE_PLL)  || ((CLK) == RCC_SOURCE_LSI)  || \
                                ((CLK) == RCC_SOURCE_LSE))
/**
  * @}
  */
  
/** @defgroup RCC_HSI_CLK
  * @{
  */

#define RCC_HSI_16M                     ((RCC_ICSCR_HSI_FS_16Mhz) | ((*(uint32_t *)(0x1FFF1C0C)) & 0x7FF))
#define RCC_HSI_24M                     ((RCC_ICSCR_HSI_FS_24Mhz) | ((*(uint32_t *)(0x1FFF1C10)) & 0x7FF))
#define RCC_HSI_36M                     ((RCC_ICSCR_HSI_FS_36Mhz) | ((*(uint32_t *)(0x1FFF1C14)) & 0x7FF))
#define RCC_HSI_48M                     ((RCC_ICSCR_HSI_FS_48Mhz) | ((*(uint32_t *)(0x1FFF1C18)) & 0x7FF))

#define IS_RCC_HSI_CLK(CLK) (((CLK) == RCC_HSI_16M)  || ((CLK) == RCC_HSI_24M)  || \
                             ((CLK) == RCC_HSI_36M)  || ((CLK) == RCC_HSI_48M))
                           
#define RCC_HSI_CLK_Div1                (RCC_CR_HSIDIV_1)
#define RCC_HSI_CLK_Div2                (RCC_CR_HSIDIV_2)
#define RCC_HSI_CLK_Div4                (RCC_CR_HSIDIV_4)
#define RCC_HSI_CLK_Div8                (RCC_CR_HSIDIV_8)
#define RCC_HSI_CLK_Div16               (RCC_CR_HSIDIV_16)
#define RCC_HSI_CLK_Div64               (RCC_CR_HSIDIV_64)
#define RCC_HSI_CLK_Div128              (RCC_CR_HSIDIV_128)
#define IS_RCC_HSI_DIV(DIV) (((DIV) == RCC_HSI_CLK_Div1) || ((DIV) == RCC_HSI_CLK_Div2)   || \
                             ((DIV) == RCC_HSI_CLK_Div4) || ((DIV) == RCC_HSI_CLK_Div8)   || \
                             ((DIV) == RCC_HSI_CLK_Div16)||((DIV) == RCC_HSI_CLK_Div64)   || \
                             ((DIV) == RCC_HSI_CLK_Div128))
/**
  * @}
  */

/**
  * @}
  */

/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */

/* Function used to set the RCC clock configuration to the default reset state */
void RCC_DeInit(void);

/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
void RCC_HSEConfig(uint32_t RCC_HSE);
ErrorStatus RCC_WaitForHSEStartUp(void);
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
void RCC_HSICmd(FunctionalState NewState);
void RCC_LSEConfig(uint32_t RCC_LSE);
void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive);
void RCC_LSICmd(FunctionalState NewState);
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
void RCC_PLLCmd(FunctionalState NewState);
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
void RCC_MCOConfig(uint32_t RCC_MCOSource,uint32_t RCC_MCOPrescaler);

/* System, AHB and APB busses clocks configuration functions ******************/
void RCC_HSI_CLK(uint32_t HSI_CLK, uint32_t CLK_DIV);
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
uint32_t RCC_GetSYSCLKSource(void);
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
void RCC_PCLKConfig(uint32_t RCC_HCLK);
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);

/* Peripheral clocks configuration functions **********************************/
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
void RCC_RTCCLKCmd(FunctionalState NewState);
void RCC_BackupResetCmd(FunctionalState NewState);

void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_AHB2PeriphClockCmd(uint32_t RCC_IOPeriph, FunctionalState NewState);

void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_AHB2PeriphResetCmd(uint32_t RCC_IOPeriph, FunctionalState NewState);

/* Interrupts and flags management functions **********************************/
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
FlagStatus RCC_GetFlagStatus(uint32_t RCC_FLAG);
void RCC_ClearFlag(void);
ITStatus RCC_GetITStatus(uint8_t RCC_IT);
void RCC_ClearITPendingBit(uint8_t RCC_IT);

#ifdef __cplusplus
}
#endif

#endif /* __YS32F030_RCC_H */

/**
  * @}
  */

/**
  * @}
  */ 

/**
  * @}
  */ 

